Yield intelligence from inspection event to root-cause alert
KLARF in. Root-cause evidence package out. On-premise. Within 12 minutes of wafer map generation.
Defect data exists. It is not connected.
Yield engineers and process integration managers at semiconductor fabs and OSAT providers running 14nm and below nodes face the same structural problem: defect excursions are identified days after the damage is done. Wafer maps sit inside inspection tools. Correlation to electrical test requires manual query scripts. Root-cause triage consumes 40 to 60 engineer-hours per excursion. Scrap is discovered at probe, not at inline inspection.
The data needed to catch excursions early already exists inside every modern fab. KLA Surfscan tools write KLARF files on every wafer pass. WAT probe testers record STDF results on every tested lot. MES systems log equipment, chamber, recipe version, and shift. None of these systems talk to each other automatically. The bottleneck is the missing pipeline — a system that joins defect events to electrical outcomes and equipment lineage in real time, not in a next-morning batch report.
For fabs on 14nm and below nodes, defect excursions that go undetected for 48 hours propagate through multiple critical process steps before they are flagged. By the time probe results confirm a yield loss, hundreds of wafer starts have passed through the affected process step. The economics are straightforward: earlier detection means smaller excursion scope, fewer scrapped lots, and faster return to specification.
From inspection event to engineer alert in 12 minutes
Wafercadence connects raw inspection file output to a root-cause evidence package through three sequential processing stages, all running on-premise inside your fab network.
Data Ingestion
Raw KLARF files from KLA Surfscan and CDSEM tools are ingested as they are written by the inspection tool — no polling delay. Optical wafer scanner CSV exports from ASML HMI and Lam Seguro tools are picked up via configured file-watch paths. WAT probe test results in STDF format arrive via direct file-drop or SECS/GEM host interface. MES lot metadata is pulled via SECS/GEM or file-drop integration, providing equipment ID, chamber, recipe version, and shift data for every lot in the ingestion queue.
Classification and Correlation
A per-node CNN classifier labels each defect by defect family and confidence score. A spatial pattern engine detects edge-ring, center-spot, arc, and scratch signatures in wafer maps at counts as low as 3 occurrences per lot. A multi-layer correlation engine joins defect events to WAT and probe electrical results, tracing kill defects back to the originating layer. Equipment attribution links defect clusters to chamber ID, recipe version, and shift, generating a ranked root-cause evidence package with confidence scores on each hypothesis. All computation runs on customer-provisioned on-premise GPU hardware — inference on an NVIDIA A30 completes in 43 milliseconds per wafer map.
Alert and Disposition
A timestamped alert package is delivered to engineer email and Slack within 12 minutes of the inspection event. The package contains: a defect map annotated with spatial pattern classification, a layered correlation chart linking defect source layer to electrical kill yield, the top-3 ranked equipment hypotheses with confidence scores, and a batch-disposition recommendation (hold, continue, or quarantine). The alert package is structured so the receiving engineer can confirm or override the recommendation without pulling any additional data. SPC chart feeds are updated in parallel via SECS/GEM events.
Six capabilities that close the loop from inspection to action
Inline Defect Classification
CNN-based per-defect labeling at 97.3% accuracy across 14nm and below nodes
The classification engine ingests KLARF and optical scanner files as they are written by the inspection tool, with no polling delay. Each defect image patch is run through a convolutional neural network trained per process node and defect family — bridging, particle, scratch, pit, pattern anomaly, and more. Confidence scores are returned with each label, letting engineers filter on high-confidence calls or review borderline cases in a unified queue. The model is retrained quarterly on customer-specific review images, so accuracy compounds as Wafercadence learns the fab's specific defect morphology. At 43ms per wafer map on an on-premise NVIDIA A30, latency does not add to your cycle time.
Spatial Pattern Recognition
Detects edge-ring, center-spot, arc, and scratch signatures at counts as low as 3 defects per lot
Most spatial pattern tools require dozens of defects before a distribution fires an alert. Wafercadence uses a geometric kernel on the wafer coordinate frame to detect radial, linear, and arc signatures at statistically early counts — often 3 to 5 defects on a single wafer. This matters at advanced nodes where a single contamination event can produce a tight cluster that kills yield on a localized zone of each die. When a spatial signature is matched, the pattern is overlaid on the die map and correlated to prior excursions with the same geometry, giving engineers a library reference point within the first notification.
Yield Correlation Engine
Joins inline defect events to WAT probe electrical data to find which layers are actually killing yield
Defect count without electrical context is noise. The Yield Correlation Engine matches lot IDs across inspection records and STDF probe test results to compute a kill-rate per defect family per layer. The output is a ranked layer contribution chart — which layers are the primary electrical yield detractors on each product, and which defect families within those layers have the highest kill probability. For fabs running design-rule-check (DRC)-clean excursions, this layer-to-kill attribution is the first quantitative proof of which tool or process step is responsible. No SQL, no manual join scripts.
Fab-Wide Lineage Tracking
Traces every defect cluster to equipment ID, chamber, recipe version, and shift
When a spatial pattern fires, engineers need to know which specific tool chamber produced it, which recipe version was active, and which shift ran the lot. Wafercadence maintains a lineage index keyed on lot ID and wafer sequence, joining inspection timestamps to MES equipment records in real time. Equipment attribution is presented as a ranked hypothesis list: the top three chamber-recipe pairs statistically associated with the current excursion pattern, ranked by defect signature overlap with prior events from the same tool. This turns root-cause triage from a 40-hour manual exercise to a 30-minute confirmation workflow.
SPC-APC Integration
Feeds spatial defect statistics back into existing SPC charting and APC setpoint loops
Wafercadence does not replace your existing statistical process control or advanced process control infrastructure. It augments it. Per-wafer spatial defect statistics — mean defect density, pattern severity score, layer contribution ratios — are pushed to SPC chart feeds via standard SECS/GEM events or file-drop to your MES. When pattern severity exceeds a configurable threshold, a setpoint-adjustment recommendation is generated and forwarded to the relevant APC module, flagged for engineer confirmation before execution. This closes the loop between inspection data and process actuation without requiring manual intervention for routine adjustments.
Air-Gap On-Premise Deployment
All inference runs inside your fab network — wafer images and lot metadata never leave your facility
Wafer defect images contain process IP: layer stack, die pattern density, and defect morphology are all fingerprints of a fab's process recipe. Wafercadence is architected for zero external data egress. The classifier, correlation engine, and lineage tracker all run on customer-provisioned on-premise GPU hardware inside the fab network boundary. Wafercadence engineers deploy the system on-site, configure the SECS/GEM and MES interfaces, and validate the alert pipeline — then leave. Model updates are delivered as signed container images over a one-way pull channel; no outbound data port is required.
Connects to your existing inspection and MES stack
Built for yield engineers at fabs running 14nm and below
Wafercadence is designed for yield engineers and process integration managers at semiconductor foundries and OSAT providers running 14nm and below nodes. The platform is built for facilities with 10,000 to 30,000 wafer starts per month, typically employing 15 to 80 yield engineers who are responsible for excursion response and root-cause triage.
Our customers are teams that already operate inspection tools, WAT probe testers, and an MES — and who are spending significant engineer-hours manually correlating data across those systems. Wafercadence replaces the manual correlation workflow with a real-time pipeline, while keeping all data on-premise.
The platform is optimally suited to teams evaluating AI yield tooling on a contained production area before a broader rollout. The Pilot tier is designed for this evaluation scenario — a single fab line or OSAT site, with a contained inspection data feed and direct access to the engineering team during onboarding.
Request an engineering demo against your actual tool stack
Bring your KLARF file samples and your current triage process. We will show you the classification output, the spatial pattern detection, and the layer-to-kill correlation running on data that looks like yours — not generic demo data.
Request Engineering Demo