Precision by engineers, for engineers.
Wafercadence was founded in San Jose in 2024 by a process engineer who spent 13 years watching the same excursion cycle repeat. The platform is built for yield engineers who work in minutes, not the IT buyers who approve 18-month deployment timelines.
How Wafercadence started.
Kenji Nakamura joined his first fab in 2011 as a process integration engineer, working on CMOS yield programs at logic nodes from 28nm down. Over 13 years at two logic facilities and one DRAM memory fab in the San Jose–Milpitas corridor, he worked through hundreds of excursion cycles — and watched the same failure mode repeat almost every time.
A particle excursion would generate two or three wafer maps with the same edge-ring signature, the FDC system would log a CMP chamber pressure deviation at nearly the same timestamp, and the SPC chart for the same tool would show a Cpk crossing 1.0. All three signals were in separate systems with separate database passwords and no common lot ID linking them. The engineering post-mortem that finally connected those dots would finish on Friday — four days after the excursion, and after another 35 to 50 wafer starts had entered the affected diffusion module.
The data to find the root cause in 12 minutes had been there on Monday morning. What was missing was a platform that could cross-correlate KLARF coordinates, FDC events, and SPC parameters in real time — on the fab's own hardware, with no change control and no cloud vendor access agreement attached to the architecture. In late 2024, Nakamura left his role as a Senior Process Integration Engineer and founded Wafercadence in San Jose to build that platform.
We are not building a general manufacturing analytics tool or a cloud-based quality management system. Every feature maps directly to a decision a yield engineer makes on the fab floor — from the evidence package format to the 72-hour lookback window to the air-gapped deployment path. That specificity is intentional.
Four engineers with one focus.
13 years as a process integration engineer across logic and memory nodes, with direct responsibility for D0 reduction programs at 28nm and 14nm. Founded Wafercadence in San Jose in 2024 after watching excursion data sit uncorrelated in disconnected systems through too many post-mortems.
10 years in fab process integration, focused on in-line defect reduction and excursion containment at 28nm and below. Specialist in spatial pattern classification — she built the internal defect clustering methodology that became the foundation for the Wafercadence wafer map analysis module.
SECS/GEM and MES integration specialist with 8 years of on-premise fab infrastructure work, including SECS-II/HSMS connector development for a logic foundry's MES migration from Workstream to a custom in-house system. Architect of the Wafercadence ingest layer and connector table.
Computational science background with 6 years applied to semiconductor inspection data. Built the CNN-based spatial pattern classifier that sits at the core of the Wafercadence defect analysis pipeline — trained on KLARF coordinate sets from multiple process nodes, achieving 97.3% pattern classification accuracy at 14nm and below.
Three rules we don't break.
Speed of evidence, not speed of alerts. A 12-minute alert that arrives without a ranked evidence package — spatial pattern, chamber attribution, lot quarantine list — still requires 4 days of manual work. We deliver both.
Fabs don't change what's working. We do not require you to replace your MES, upgrade your inspection tools, or reroute your SPC data. Wafercadence reads from your existing KLARF files, SPC database, and FDC stream. SECS/GEM or file-drop. No change control for basic ingest.
Your wafer data never leaves your facility. On-premise deployment, air-gapped option available. No telemetry to external endpoints. No cloud data pipeline. Wafercadence was designed on-premise first — not ported from a SaaS architecture after the fact.
From the Field
"We went from a 4-day post-mortem cycle to a 12-minute alert-to-action window. Wafercadence found the chamber 3B attribution in our CMP excursion before the next lot entered the module."
— Yield Engineering Manager, logic fab
"The SECS/GEM integration was done in a single shift. No change control, no downtime. It reads from our existing KLA inspection export and correlates against WAT data we were already collecting."
— Process Integration Engineer, memory facility
Start a technical conversation.
Our yield engineering team reviews every inquiry. Bring your inspection data format — we'll have a real conversation, not a sales script.