GLOSSARY

Semiconductor yield engineering terminology.

A-Z reference for the vocabulary used by process engineers, yield teams, and OSAT quality managers — from D0 and kill ratio to KLARF, SECS/GEM, and GEM300.

30+

Terms defined and cross-referenced

A–W

Full alphabetic index coverage

A

APC (Advanced Process Control): A framework for using process data to automatically adjust equipment set-points in real time or run-to-run, reducing process variation and improving yield. Often paired with SPC and FDC systems.

B

Bin map: A color-coded map of die on a wafer showing the electrical test bin result for each die. Used in OSAT to visualize sort yield and identify spatial patterns in test failures.
Bin sort yield: The fraction of die that pass electrical test at wafer probe sort, categorized by bin number (e.g., Bin 1 = pass, Bin 5 = fail for specific fault category). Compared against final test yield in OSAT correlation.

C

Cpk (Process Capability Index): A statistical measure of how well a process fits within its specification limits, accounting for the mean offset from the target. Cpk > 1.33 is typically required for production. Reflects short-term capability within a single run.
Chamber matching: The practice of aligning process performance across multiple chambers in a multi-chamber tool to ensure equivalent output. Requires establishing a golden chamber reference and qualifying other chambers to match its process signature.
Commonality analysis: A root-cause analysis technique that identifies factors common to failing wafers or lots — such as chamber ID, slot position, operator shift, or recipe version — by cross-referencing inspection events with process context data.

D

D0 (Defect Density): The number of defects per unit area of silicon wafer, typically expressed as defects/cm². D0 is a key yield predictor: lower D0 correlates with higher die yield. Tracked over time as the yield learning curve.
Die yield: The fraction of die on a processed wafer that pass all electrical tests. Die yield = (passing die) / (total die on wafer). Directly related to D0 and kill ratio through models such as the Poisson or Seeds yield models.

E

EWMA (Exponentially Weighted Moving Average): A statistical filter that gives more weight to recent data points and less to older ones. Used in SPC and APC to detect gradual process drift that would be missed by a simple moving average or Shewhart control charts.
Excursion: An abnormal deviation in a process parameter or yield metric outside established control limits. Excursions require immediate investigation and containment to prevent yield loss propagation to subsequent lots.

F

FDC (Fault Detection and Classification): A system that monitors equipment sensor data during processing to detect faults in real time and classify their severity. FDC enables immediate alarm and recipe abort when process parameters drift outside control limits, reducing the number of lots processed during an excursion.

G

GEM300: The SEMI standard E148 specification for 300mm wafer equipment communication, built on SECS/GEM (E40/E90/E94/E30). GEM300 defines enhanced capabilities for process program management, substrate tracking, and remote control specific to 300mm equipment.
Golden chamber: A reference chamber in a multi-chamber tool that sets the performance benchmark for chamber qualification. Other chambers are tuned and qualified to match the process output of the golden chamber.

K

Kill ratio: The probability that a defect at a given process layer will cause a die failure at electrical test. Kill ratio connects in-line defect inspection data to final sort yield — a defect type with kill ratio 0.6 will cause ~60% of affected die to fail. Used to prioritize yield improvement efforts by layer.
KLARF (KLA Results File): A standardized file format for wafer inspection data output by KLA-Tencor (now KLA) inspection tools. KLARF files contain defect coordinates, defect size, defect type, and wafer orientation information. Widely used as the de facto format for sharing inspection data between tools and analysis systems.

M

MES (Manufacturing Execution System): The software system that manages and tracks work-in-progress at a fab — lot tracking, recipe dispatch, equipment scheduling, and process history. Common fab MES vendors include Workstream (Applied Materials) and Camstar (Siemens).

O

OEE (Overall Equipment Effectiveness): A composite metric for equipment productivity = Availability × Performance × Quality. In semiconductor manufacturing, OEE combines uptime, throughput rate vs. theoretical rate, and first-pass yield to give a single equipment health number.
OSAT (Outsourced Semiconductor Assembly and Test): Companies that perform semiconductor packaging and electrical testing for fabless chip designers and IDMs. OSAT facilities handle die sort, wire bonding, flip-chip assembly, final test, and shipping. Major OSAT providers include ASE, Amkor, and JCET.

P

Pareto analysis: A ranked frequency distribution technique that identifies the most significant yield loss contributors. In semiconductor yield, a Pareto chart of defect types or equipment IDs typically reveals that 20% of causes drive 80% of yield loss.
Ppk (Process Performance Index): Like Cpk, but calculated using the total (long-term) process standard deviation including run-to-run variation. Ppk < Cpk indicates that between-run or lot-to-lot variation is significant — an important distinction for process stability assessment.

R

RtR (Run-to-Run control): A form of APC that adjusts recipe set-points between process runs (lots or wafers) based on measurements from the previous run. RtR control reduces drift and offset in processes such as CMP, etch, and lithography overlay.

S

SECS/GEM (SEMI Equipment Communications Standard / Generic Equipment Model): The SEMI standard protocol stack for communication between semiconductor manufacturing equipment and host systems. SECS-II defines the message format; HSMS defines the TCP/IP transport layer; GEM (E30) defines the expected behaviors and state machines. The standard interface for MES-to-tool communication.
SPC (Statistical Process Control): A quality methodology that uses statistical methods and control charts to monitor and control a process, ensuring it operates at its full potential. In semiconductor manufacturing, SPC monitors parameters such as film thickness, etch depth, overlay, and CD against control limits derived from historical data.
Spatial pattern classification: The identification of non-random defect distributions on a wafer map — edge ring, center spot, arc, scratch, donut, random scatter — as diagnostic indicators of specific equipment failure modes or process excursions. Systematic patterns indicate a deterministic equipment cause; random patterns indicate contamination or particle events.

W

Wafer map: A visual representation of a wafer divided into individual die, showing inspection results, electrical test bin assignments, or other spatial data per die. Wafer maps are the primary tool for identifying systematic vs. random yield loss patterns.
WAT (Wafer Acceptance Test): Electrical tests performed on dedicated test structures (not product die) across the wafer to verify that process parameters are within specification. WAT data serves as an early indicator of parametric yield before full product sort. Also called PCM (Process Control Monitor) at some fabs.

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