Engineers who lived the problem.

13 years as a process integration engineer across logic and DRAM memory nodes, running D0 reduction programs at 28nm and 14nm. Founded Wafercadence in 2024 after observing that every fab he worked in had the same problem: all the data to catch an excursion in 12 minutes existed — uncorrelated — across three different systems.

10 years in fab process integration, with hands-on responsibility for in-line defect density reduction at 28nm and 16nm logic nodes. Built the internal defect clustering methodology that became the basis for the Wafercadence spatial pattern classifier. Leads all yield engineering customer deployments.

SECS/GEM and MES integration specialist with 8 years building on-premise data infrastructure at a 300mm logic foundry, including SECS-II/HSMS connector development and lot traveler schema work. Architect of the Wafercadence ingest layer and all MES connector implementations.

Computational scientist with 6 years applying image classification methods to semiconductor inspection data. Designed and trained the CNN-based spatial pattern classifier for the Wafercadence wafer map module — achieving 97.3% defect pattern classification accuracy at 14nm and below. Leads all model validation and release qualification.